The present invention relates to the field of semiconductor electronic devices and a method for manufacturing the same. More particularly, the present invention relates to a process ideally suited for manufacturing erasable programmable read-only memory cells.
Erasable programmable read-only memory (EPROM) technology is known for use in both memory and programmable logic applications. In particular, EPROMs are implemented using floating gate field effect transistors in which the binary states of the EPROM cell are represented by the presence or absence of sufficient charge on the floating gate to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
In the traditional and most basic form, EPROMs are programmed electrically and erased by exposure to ultraviolet light, and are typically referred to as ultraviolet erasable programmable read-only memories (UVEPROMs). As seen in FIG. 1, a UVEPROM cell typically includes a storage transistor 10 having two polysilicon gates disposed above a P-doped substrate 12 with a pair of spaced-apart N-doped active regions 14 and 16 defining a channel region 18 therebetween. The two polysilicon gates are disposed above the channel region 18 with the opposing ends of each of the polysilicon gates overlapping one of the active regions 14 and 16. One gate is disposed between the remaining gate and the substrate 12, defining a floating gate 20. The remaining gate is spaced apart from the floating gate 20 and defines a control gate 22. The floating gate 20 is embedded in an oxide 24 which facilitates capacitive coupling to both the control gate 22 and the substrate 12. A UVEPROM cell is programmed by running a high current between the active regions 14 and 16 while applying a positive potential to the control gate 22. This is typically achieved by grounding one of the active regions, such as the source 14, while applying the positive potential to both the control gate 22 and the remaining active region, the drain 16. In this fashion, electrons in the substrate 12 obtain sufficient energy to overcome the 3.2 eV energy barrier at the interface between the silicon substrate and the silicon dioxide. This phenomenon is typically called electron injection. The positive voltage on the floating gate 20 causes the electrons to collect thereon. The cell 10 is erased by internal photo emission of electrons from the floating gate 20 to the control gate 22 and the substrate 12. Ultraviolet light increases the energy of the floating gate electron to a level where they jump the 3.2 eV energy barrier and return to the substrate 12.
Another form of EPROM is the electrically erasable programmable read-only memory (EEPROM or E2PROM), commonly referred to as flash EPROMs. Storage transistors for flash EPROMs generally include two serially connected N-channel metal oxide semiconductor transistors in which one of the transistors has an additional gate that is floating and is sandwiched between a control gate and a channel. This floating gate is used to store positive or negative charges which determine the state of the flash EPROM. The other transistor is used for selection purposes. The electrons transfer between the floating gate and the drain by Fowler-Nordheim tunneling. This is a quantum mechanical phenomenon that allows electron to pass through the aforementioned silicon substrate-silicon dioxide interface at an energy below 3.2 eV. Programming of the cell is achieved by tunneling from the floating gate to the drain, leaving the floating gate relatively more positively charged. In the erase mode, the control gate is at a high voltage and the drain is grounded. A drawback with Fowler-Nordheim tunneling is that it often results in over-erase of the flash EPROM cell which tends to leave the floating gate positively charged.
To overcome the over-erase problem associated with Fowler-Nordheim tunneling, a flash EPROM cell employing a split gate storage transistor 26, shown in FIG. 2 was developed. The split gate transistor 26 merges the control gate 28 with the floating gate 30 over the channel 32. The split gate transistor 26 is characterized by the control gate 28 having a first conductive region 34 which extends parallel to both the channel 32 and the floating gate 30 and a second region 36 which extends from the first conductive region 34, transversely thereto toward the channel 32. The second conductive region 36 prevents the cell from xe2x80x9cturning-onxe2x80x9d as a result of positive charge on the floating gate 30. As before, the floating gate is embedded in an oxide layer 38 so as to be capacitively coupled to both the control gate 28 and the channel region 32.
A problem encountered with the manufacture of flash EPROMs concerned variations in the dimensions of the oxide layer. Specifically, areas of the oxide layer are formed so that they are relatively thin resulting in sharp needle-like protrusions that extend from the surface of the polysilicon gate into the thermal oxide. This results from oxidation progressing faster along certain crystal directions, e.g., at the intersection of two surfaces extending transversely to one another. Electric fields concentrate at the tips of these protrusions which support enhanced localized conduction as much as an order of magnitude greater than in protrusion-free silicon surfaces.
Recent trends in flash EPROM design have employed thermal techniques to control the size and shape of these protrusions. In this fashion, silicon oxide layers having a greater over-all thickness may be employed while still providing Fowler-Nordheim tunneling. However, controlling the size and shape of these protrusions is particularly problematic with the split gate cell design as it may cause shorting between the gates in a worse case and can make charge retention in the floating gate problematic which causes premature erasing of the cell in the most harmless case.
What is needed, therefore, is a flash EPROM cell and method for manufacturing the same, which allows precise control of the thickness of dielectric oxide layers positioned between the control and floating gates.
The present invention provides a split gate transistor for an EPROM cell and a method for forming the same that includes forming a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. An exemplary embodiment of the EPROM cell is formed atop a silicon substrate and includes a first oxide region disposed on the substrate, and a first region of conductive material disposed adjacent to the first oxide region that extends coextensive therewith. The first oxide region is typically formed from silicon dioxide and the first conductive region is formed from polysilicon. The first conductive layer has a surface disposed adjacent to the first oxide region and two spaced-apart edges extending transversely to the surface. A plurality of side-wall spacers are provided, each of which is in abutting relationship with one of the minor surfaces. A first portion of each of the plurality of side-wall spacers is formed from a single layer of material, defining a single-wall portion. A second portion of each of the plurality of side-wall spacers includes two layers of differing materials, defining a double-wall portion. An oxide-nitride-oxide composite is typically employed to form the single wall portion as well as one of the layers of the double-wall portion. The remaining layer of the double wall portion is formed from silicon nitride. Disposed adjacent to the plurality of sidewall spacers, as well as the major surface, is an additional oxide region. A second conductive region is disposed adjacent to, but spaced apart from, the first conductive region. The first conductive region is disposed between the substrate and a first segment of the second conductive region, with a second segment of the second conductive region extending from the first segment, transversely thereto toward the substrate. In this fashion, the first conductive region forms the floating gate and the second conductive region forms the control gate of the split gate storage transistor.
The split gate transistor is constructed by forming, on a substrate, the first oxide region and then forming, on the oxide region, a first region of conductive material having a major surface and two spaced-apart minor surfaces extending transversely to the major surface. A second oxide region is formed in abutting relation with the major surface and the spaced-apart minor surfaces. The second oxide region is covered with a nitride region. Thereafter, a portion of the second oxide region and a segment of the nitride region, both of which are positioned proximate to the major surface, are removed so as to expose the first major surface. The segment of the nitride region removed also includes areas of the nitride region disposed adjacent to the minor surfaces. In this manner, spacers are formed in abutting relation with the minor surfaces so as to have a single wall portion and a double wall portion. Subsequent to the formation of the spacers, an additional oxide region is formed adjacent to the major surface followed by the formation of a conductive region adjacent to, but spaced apart from, the region of first conductive material. Providing spacers having differential composition facilitates control of the dielectric surrounding the floating gate and, therefore, the distance between the floating gate and the control gate and reducing leakage of the charge from the floating gate, thereby improving the charge retention properties of the storage transistor.